For intelligent communication to take place at the Physical layer, the transmitter and the receiver must be synchronized—that is, the receiver must know when to sample the channel to detect the presence of a valid signaling event. If the receiver samples too soon or too late, erroneous data will result. In such cases, 0s may be falsely interpreted as 1s and vice versa. The following discussion explores timing issues in both parallel and serial Physical layer environments.

Timing in Parallel Physical Interfaces

The issue of synchronization in parallel Physical layer environments is actually quite simple. Referring back to Figure 4-4, we see that, among the multiple communications paths between the transmitter and the receiver, the clock path is used to synchronize the two communicating parties. Using the clock circuit, the transmitter explicitly indicates to the receiver when valid data are present on the data circuits. If data rates and interface distances are held within limits to ensure that skew does not occur, the information supplied by the clock circuit is adequate to avoid erroneous sampling of the data circuits.

Timing in Serial Physical Interfaces

When only one path is available for communication between a transmitter and a receiver, the issue of synchronization becomes more complex. There are basically two ways to synchronize a transmitter and a receiver in a serial environment. One relies on implicit timing between communicating parties and is called asynchronous communication, while the other is based on the exchange of explicit timing information between communicating parties and is called synchronous communication.